Logic level testing of a system at IBM during development of the final manufacturing process of integrated circuits used in the mainframe activities of the company now sold as S/ 390 system has been researched since the 1970's, see for instance, E. B. Eichelberger, "Method of Level Sensitive Testing a Functional Logic System," U.S. Pat. No. 3,761,695, Sep. 25, 1973,and E. B. Eichelberger and T. W. Williams, "A Logic Design Structure for LSI Testability," Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 462-468. See also U.S. Pat. No. 5,764,655: "Built in Self Test with Memory," granted Jun. 9, 1998, as discussed below.
Historically, scan chain fails have been difficult to diagnose. There are some applications which are useful in this area, but they have a low success rate and typically require additional data collection at the tester along with requiring the generation of additional patterns. All this additional work takes time and involves additional tester resources which are also expensive.
However, we know of no successful look ahead method for testing and diagnosing broken or stuck-at scan chains to a failing Shift Register Latch (SRL). This problem is usually encountered early in the life cycle for new chip technology development for improving the process so that manufacturing yield levels are quickly achieved. An inability to improve the technology and yield the device can greatly impact a program or at least severely minimize the revenue that could be realized in a given product life cycle. So, improvement of the technology development life cycle with a method for rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct the process anomalies as is achieved by our method described below.